As semiconductor devices have become more highly integrated, the size of active regions therein has been reduced. In some semiconductor devices, the channel region of a MOS transistor can be constrained to sub-micro lengths. As the length of the channel region becomes smaller, the source/drain regions of the MOS transistor can have a larger electrical influence on depletion layers that are adjacent to the source/drain regions. This influence can be referred to as a short channel effect.
One short channel effect is to decrease the threshold voltage Vt of a MOS transistor. The decreased threshold voltage Vt due to short channel effect can be associated with an electric field and electric potential distribution in the depletion layers of the transistor as well as a voltage applied to a gate electrode of the MOS transistor.
Another example of the short channel effect is a decrease in the breakdown voltage between the source/drain regions. The width of the depletion layer adjacent to the drain region is proportional to the drain voltage, such that the depletion layer adjacent to the drain region can become close to the depletion layer adjacent to the source region. As the length of the channel region is shortened, the depletion layers of the drain region and source region can overlap (e.g., become electrically connected) so that an electric field in the drain region can then influence the source region and the electric potential available to diffuse electrons in the source region is thereby lowered. Consequently, although the channel region doesn't extend between the source/drain regions, a current nevertheless can flow between the source/drain regions. This effect can be referred to as punch-through. When punch-through occurs, a current that flows through the drain region can substantially increase without the transistor operating in a saturated region.
To increase the memory capacity of a semiconductor device, such as a dynamic random access memory (DRAM) device, unit cells may be formed in small areas of a substrate. To obtain a predetermined capacitance level for a cell capacitor, the length of the gate electrode can be shortened to form a highly-integrated cell. A short channel effect may occur as the length of the channel region is shortened in proportion to shortening of the length of the gate electrode, which may cause a decrease in the threshold voltage and increase in the leakage current of the cells. In highly integrated cells, adjacent gate electrodes are closely spaced. Forming a miniature contact between closely spaced adjacent gate electrodes can be very difficult.
In an attempt to reduce the short channel effect and improve the refresh characteristics of a cell transistor, some transistors have included a recessed channel. A recessed channel may allow a transistor to have an elongated gate electrode length without increasing a horizontal area of the gate electrode. The transistor can include a gate electrode that is formed in a trench in a surface portion of a substrate. The recessed channel can be formed along an inner wall and bottom face of the trench.
A transistor having a recessed channel can be formed by forming an isolation layer on a substrate to divide the substrate into an active region and a field region. A trench for a gate electrode is formed in the active region. A hard mask layer is formed on the active region and the field region.
An organic anti-reflective layer is the formed on the hard mask layer. The hard mask layer is patterned by a conventional etching process. The organic anti-reflective layer may partially remain on a lower surface of the hard mask layer. The hard mask layer may not be completely removed from locations where a gate trench is to be formed.
The hard mask layer may have an etching selectivity higher than that of an underlying layer that is to etched. Thus, a portion of the substrate on which the hard mask layer partially remains may not be etched so that the uniformity of the gate trench becomes affected.
FIG. 1 is a scanning electron microscope (SEM) picture that illustrates a hard mask layer pattern that partially remains in a region in which a gate trench is formed.
Referring to FIG. 1, a hard mask layer pattern 1 partially remains on a central portion of a gate trench so that the gate trench is entirely exposed through the hard mask layer pattern 1.
FIGS. 2 and 3 are SEM pictures illustrating a substrate that is etched using the hard mask layer pattern in FIG. 1 as an etching mask.
As shown in FIGS. 2 and 3, since the hard mask layer pattern 1 partially remains on the central portion of the gate trench, an edge portion 2b of the gate trench has a normally etched configuration. In contrast, a central portion 2a of the gate trench is not etched so that the central portion of the gate trench is not uniform (i.e., an abnormally etched configuration).